HANBit
Input hold time
CLK to output in Low-Z
CAS
CLK to output
latency=3
CAS
in Hi-Z
latency=2
t
SH
t
SLZ
t
SHZ
-
-
6
0.8
1
5.4
1
1
6
1
1
6
HSD32M72D18A
1
1
6
7
ns
ns
ns
ns
3
3
2
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered
ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Self
refres
h
Entry
Exit
CKE
n-1
H
H
L
H
CKE
n
X
H
L
H
X
/C
E
L
L
L
H
L
/R
A
S
L
L
H
X
L
/C
A
S
L
L
H
X
H
/W
E
L
H
H
X
H
D
Q
M
X
X
X
X
V
BA
0,1
A10/
AP
OP code
X
X
Row address
L
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A9)
Column
L
H
precharge
H
Bank selection
All banks
Entry
Exit
Entry
Exit
H
H
L
H
L
H
H
X
H
L
X
X
L
H
L
H
L
L
H
L
X
H
L
H
L
L
L
X
V
X
X
H
X
V
X
X
H
X
H
X
H
H
H
X
V
X
X
H
X
V
L
L
X
V
X
X
H
X
V
X
X
X
X
X
X
X
V
X
X
X
7
V
X
L
H
X
X
L
H
L
L
X
V
H
X
X
Address
(A0 ~ A9)
4,5
6
4
4,5
4
A11
A9~A0
NOTE
1,2
3
3
3
3
Bank active & row addr.
Read &
column
address
Auto
disable
Auto
disable
Auto
disable
Auto
disable
Burst Stop
Precharge
precharge
precharge
precharge
Write &
column
address
Clock suspend or
active power down
Precharge
down mode
DQM
power
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
URL: www.hbe.co.kr
REV.1.0 (August.2002)
-8-
HANBit Electronics Co.,Ltd.
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
