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HSD32M72D18P-12 参数 Datasheet PDF下载

HSD32M72D18P-12图片预览
型号: HSD32M72D18P-12
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模组256Mbyte ( 32Mx72bit ) ,与DIMM ECC基于16Mx8 , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 11 页 / 179 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
CKE
V
IH
(min)
I
CC2
NS
CLK
V
IL
(max),
t
CC
=∞
126
HSD32M72D18P
Input signals are stable
Active standby current in
power-down mode
I
CC3
P
I
CC3
PS
CKE
V
IL
(max), t
CC
=10ns
CKE&CLK
V
IL
(max)
t
CC
=∞
CKE≥V
IH
(min),
I
CC3
N
CS*≥V
IH
(min),
t
CC
=10ns
540
mA
90
mA
90
Active standby current in
non power-down mode
(One bank active)
Input signals are changed
one time during 20ns
CKE≥VIH(min)
I
CC3
NS
CLK
≤VIL(max),
t
CC
=∞
360
Input signals are stable
I
O
= 0 mA
Operating current
(Burst mode)
I
CC4
Page burst
4Banks Activated
t
CCD
= 2CLKs
Refresh current
I
CC5
t
RC
t
RC
(min)
396
3960
0
27
14.4
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
mA
mA
3780
3780
mA
2
270
2610
0
2250
2250
mA
1
Self refresh current
I
CC6
CKE
0.2V
AC OPERATING TEST CONDITIONS
(vcc = 3.3V
±
0.3V, TA = 0 to 70° C)
PARAMETER
AC Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
UNIT
V
V
ns
V
+3.3V
V
tt
=1.4V
1200Ω
D
OUT
870Ω
URL: www.hbe.co.kr
REV.1.0 (Augsut.2002)
50Ω
D
OUT
Z0=50Ω
50pF
50pF*
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
-6
-
HANBit Electronics Co.,Ltd.