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HSD8M32B4 参数 Datasheet PDF下载

HSD8M32B4图片预览
型号: HSD8M32B4
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模块32Mbyte ( 8M ×32位)的基础上4Mx16 , 4Banks , 4K参考144pin SO -DIMM 。 , 3.3V [Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) 144pin SO-DIMM based on 4Mx16, 4Banks, 4K Ref., 3.3V]
分类和应用: 动态存储器
文件页数/大小: 11 页 / 108 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HSD8M32B4
Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) 144pin SO-DIMM based on
4Mx16, 4Banks, 4K Ref., 3.3V
Part No. HSD8M32B4
GENERAL DESCRIPTION
The HSD8M32B4 is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of
four CMOS 1M x 16 bit x 4banks Synchronous DRAMs in TSOP-II packages mounted on a 144-pin, FR-4-printed circuit
board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The
HSD8M32B4 is a SO-DIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O
transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high performance memory system applications All module components
may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
Part Identification
HSD8M32B4-10 : 100MHz ( CL=2)
HSD8M32B4-10L : 100MHz ( CL=3)
HSD8M32B4-12 : 125MHz ( CL=3)
HSD8M32B4-13 :133MHz ( CL=3)
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±0.3V
power supply
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge
of the system clock
FR4-PCB design
The used device is K4S641632D-TC
URL:www.hbe.co.kr
REV.1.0 (August.2002).
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HANBit Electronics Co.,Ltd