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HSD8M64D4B-13 参数 Datasheet PDF下载

HSD8M64D4B-13图片预览
型号: HSD8M64D4B-13
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM模块64Mbyte ( 8Mx64位) , DIMM , 4Banks , 4K参考, 3.3V [Synchronous DRAM Module 64Mbyte (8Mx64-Bit), DIMM, 4Banks, 4K Ref., 3.3V]
分类和应用: 存储动态存储器
文件页数/大小: 11 页 / 85 K
品牌: HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
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HANBit
HSD8M64D4B
Synchronous DRAM Module 64Mbyte (8Mx64-Bit), DIMM, 4Banks,
4K Ref., 3.3V
Part No. HSD8M64D4B
GENERAL DESCRIPTION
The HSD8M64D4B is a 8M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of
four CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate.
Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M64D4B
is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous
design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high
performance memory system applications All module components may be powered from a single 3.3V DC power supply
and all inputs and outputs are LVTTL-compatible.
FEATURES
Part Identification
HSD8M64D4B-10
HSD8M64D4B- 13
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±0.3V
power supply
MRS cycle with address key programs
- Latency (Access from column address)
- Burst length (1, 2, 4, 8 & Full page)
- Data scramble (Sequential & Interleave)
JEDEC standard
All inputs are sampled at the positive going edge of the system clock
The used device is2Mx16Bitx4Banks SDRAM
: 100MHz ( CL=2)
: 133MHz ( CL=3)
HSD8M64D4B-10L : 100MHz ( CL=3)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
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