CA555, CA555C, LM555, LM555C, NE555
Electrical Specifications
T
A
= 25
o
C, V+ = 5V to 15V Unless Otherwise Specified
(Continued)
CA555, LM555
PARAMETER
Output Rise Time
Output Fall Time
NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R
1
and R
2
to be used in Figure 4 (astable operation); the maximum total
R
1
+ R
2
= 20MΩ.
SYMBOL
t
R
t
F
TEST CONDITIONS
MIN
-
-
TYP
100
100
MAX
-
-
CA555C, LM555C, NE555
MIN
-
-
TYP
100
100
MAX
-
-
UNITS
ns
ns
Schematic Diagram
V+
8
4.7K
830
D
1
4.7K
D
2
Q
10
Q
3
Q
4
1K
5K
6.8K
THRESHOLD
COMPARATOR
TRIGGER
COMPARATOR
FLIP-FLOP
OUTPUT
Q
16
Q
19
Q
20
3.9K
OUTPUT
3
THRESHOLD
6
Q
1
Q
2
Q
5
5K
10K
CONTROL
VOLTAGE
5
2
TRIGGER
RESET
4
RESET
7
DISCHARGE
1
V-
Q
6
DISCHARGE
100
Q
8
100K
Q
9
Q
11
Q
12
Q
13
5K
Q
14
Q
7
4.7K
7K
D
3
D
4
Q
18
220
Q
17
Q
15
4.7K
Q
21
NOTE: Resistance values are in ohms.
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor C
T
is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across C
T
which drives the output voltage “high” (relay ener-
gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R
1
C
T
. When the
voltage across the capacitor equals 2/3 V+, the comparator
resets the flip-flop which in turn discharges the capacitor rap-
idly and drives the output to its low state.
8-5
HARRIS [ HARRIS CORPORATION ]
