CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Pinout
CD74HC373, CD74HCT373
(PDIP, SOIC)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC573, CD74HC573, CD74HCT573
(PDIP, SOIC, CERDIP)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagrams
CD74HC373, CD74HCT373, CD74HC573, CD74HCT573
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
G
LE
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CD74HCT573
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
G
LE
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
TRUTH TABLE
OUTPUT ENABLE
L
L
L
L
H
LATCH ENABLE
H
H
L
L
X
DATA
H
L
l
h
X
OUTPUT
H
L
L
H
Z
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2
HARRIS [ HARRIS CORPORATION ]
