HI-5040 Series
Pin Configurations Switch States are Logic “0” Input
SINGLE CONTROL
SPST
HI-5040 (50Ω)
SPDT
DPST
HI-5044 (50Ω)
HI-5042 (50Ω), HI-5050 (25Ω)
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
A
D
S
1
D
D
1
1
S
1
15
14
13
12
11
10
9
A
V-
V
A
V-
V
D
S
D
S
2
2
V-
R
R
2
2
V
V
R
L
V
V
L
L
V+
V+
V+
DPDT
HI-5046 (50Ω), HI-5046A (25Ω)
4PST
HI-5047 (50Ω), HI-5047A (25Ω)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
S
2
D
D
2
2
2
A
V-
V
A
V-
V
D
S
D
S
1
1
R
R
1
4
1
4
V
V
L
S
S
L
V+
V+
D
D
4
4
S
3
S
3
D
D
3
3
DUAL CONTROL
DUAL SPST
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
DUAL DPST
HI-5045 (50Ω), HI-5049 (25Ω)
HI-5041 (50Ω)
1
2
3
4
5
6
7
8
16
15
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1
S
D
S
1
D
D
1
1
1
1
2
3
4
5
6
7
8
A
A
A
1
1
1
14
13
12
11
10
9
V-
V
V-
V
D
S
V-
V
D
S
3
3
R
R
3
4
R
3
4
V
V
S
V
L
S
L
L
V+
V+
D
V+
D
4
4
A
S
A
A
2
2
2
S
D
S
D
D
2
2
2
2
2
2
DUAL SPST
HI-5048 (25Ω)
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2
1
19
3
20
A
1
D3
4
5
6
7
8
18
17
16
15
D
V-
V-
V
1
1
2
S
S
S3
VR
R
V
L
NC
NC
D
V+
2
S4
D4
VL
A
2
14 V+
9
10 11
12 13
NOTE: Unused pins may be internally connected. Ground all unused pins.
9-112