HD74HC4538
Reset Operation
A low voltage applied to the Reset pin always forces the Q output of the HC4538 to a low state.
The timing diagram illustrates the case in which reset occurs (20) while C
X
is charging up toward the
reference voltage of the upper reference circuit (21). When a reset occurs, the output of the reset latch goes
low (22), turning on transistor M1. Thus C
X
is allowed to quickly charge up to V
CC
(23) to await the next
trigger signal.
Retrigger Operation
When used in the retriggerable mode (Fig. 3), the HC4538 may be retriggered during timing out of the
output pulse at any time after the trigger-control circuit flip-flopw has been reset (24). Because the trigger-
control circuit flip-flop resets shortly after C
X
has discharged to the reference voltage of the lower reference
circuit (25), the minimum retrigger time, t
rr
(Switching Waveform 1) is a function of internal propagation
delays and the discharge time of C
X
:
Fig. 4 shows the device configured in the non-retriggerable mode.
Power-Down Considerations
Large values of C
X
may cause problems when powering down the HC4538 because of the amount of
energy stored in the capacitor. When a system containing this device is powered down, the capacitor may
discharge from V
CC
through the input protection diodes at pin 2 or pin 14. Current through the protection
diodes must be limited to 30 mA; therefore, the turn-off time of the V
CC
power supply must not be faster
than t = V
CC
•C
X
/(30 mA). For example, if V
CC
= 5 V and C
X
= 15 µF, the V
CC
supply must turn off no
faster than t = (5 V)•(15 µF)/30 mA = 2.5 ms. This is usually not a problem because power supplies are
heavily filtered and cannot discharge at this rate.
When a more rapid decrease of V
CC
to zero voltage occurs, the HC4538 may sustain damage. To avoid this
possibility, use an external clamping diode.
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HITACHI [ HITACHI SEMICONDUCTOR ]
