7.2 UBC Register Functions ....................................................................................... 126
7.2.1 Break Address Register A (BARA)............................................................... 126
7.2.2 Break Address Register B (BARB) ............................................................... 126
7.2.3 Break ASID Register A (BASRA)............................................................... 127
7.2.4 Break ASID Register B (BASRB)................................................................ 127
7.2.5 Break Address Mask Register A (BAMRA) ................................................... 127
7.2.6 Break Address Mask Register B (BAMRB).................................................... 128
7.2.7 Break Bus Cycle Register A (BBRA) ........................................................... 128
7.2.8 Break Bus Cycle Register B (BBRB)............................................................ 129
7.2.9 Break Data Register B (BDRB) ................................................................... 130
7.2.10 Break Data Mask Register B (BDMRB) ...................................................... 131
7.2.11 Break Control Register (BRCR) ................................................................ 132
7.3 UBC Operation ................................................................................................... 134
7.3.1 User Break Operation Flow........................................................................ 134
7.3.2 Instruction Fetch Cycle Break..................................................................... 135
7.3.3 Data Access Cycle Break ........................................................................... 136
7.3.4 Saved Program Counter (PC) Value............................................................. 137
7.3.5 Examples of Use...................................................................................... 138
7.3.6 Cautions ................................................................................................ 140
Section 8 Power-Down Modes........................................................141
8.1 Overview ........................................................................................................... 141
8.1.1 Power-Down Modes ................................................................................. 141
8.1.2 Register Configuration.............................................................................. 142
8.1.3 Pin Configuration .................................................................................... 143
8.2 Register Description............................................................................................. 143
8.2.1 Standby Control Register (STBCR)............................................................. 143
8.3 Sleep Mode ........................................................................................................ 145
8.3.1 Transition to Sleep Mode .......................................................................... 145
8.3.2 Canceling Sleep Mode .............................................................................. 145
8.4 Standby Mode..................................................................................................... 145
8.4.1 Transition to Standby Mode ....................................................................... 145
8.4.2 Canceling Standby Mode........................................................................... 146
8.4.3 Clock Pause Function............................................................................... 147
8.5 Module Standby Function ..................................................................................... 147
8.5.1 Transition to Module Standby Function ....................................................... 147
8.5.2 Clearing the Module Standby Function ........................................................ 148
8.6 Timing of STATUS Pin Changes........................................................................... 148
8.6.1 Timing for Resets .................................................................................... 148
8.6.2 Timing for Canceling Standbys .................................................................. 150
8.6.3 Timing for Canceling Sleep Mode............................................................... 151
8.7 Hardware Standby Mode........................................................................................ 153
8.7.1 Transition to Hardware Standby Mode.......................................................... 153
4
HITACHI [ HITACHI SEMICONDUCTOR ]
