HM62256A Series
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L/L-SL version.
HM62256A Series
Parameter
Symbol Min
Typ
*1
Max
Unit Test conditions
———————————————————————————————————————————————–
V
CC
for data retention
V
DR
2
—
—
V
CS
≥
V
CC
– 0.2 V, Vin
≥
0 V
———————————————————————————————————————————————–
Data retention current
I
CCDR
—
0.2
30
*2
µA
V
CC
= 3.0 V, Vin
≥
0 V
——————————————–
—
0.2
10
*3
µA
CS
≥
V
CC
– 0.2 V
———————————————————————————————————————————————–
Chip deselect to data retention time t
CDR
0
—
—
ns
See retention waveform
——————————————————————————————————––
Operation recovery time
t
R
t
RC*4
—
—
ns
———————————————————————————————————————————————–
Low V
CC
Data Retention Timing Waveform
Data retention mode
V
CC
4.5 V
t
CDR
2.2 V
V
DR
CS
0V
CS
≥
V
CC
– 0.2 V
t
R
Notes: 1
2.
3.
4.
5.
Typical values are at V
CC
= 3.0 V, Ta = +25°C and not guaranteed.
20 µA max at Ta = 0 to +40°C. (only for L-version)
3 µA max at Ta = 0 to +40°C. (only for L-SL version)
t
RC
= read cycle time.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. If
CS
controls data
retention mode, Vin levels (address,
WE, OE,
I/O) can be in the high impedance state.
11
HITACHI [ HITACHI SEMICONDUCTOR ]
