HM62W8512B Series
4 M SRAM (512-kword
×
8-bit)
ADE-203-904E (Z)
Rev. 4.0
Oct. 20, 1999
Description
The Hitachi HM62W8512B is a 4-Mbit static RAM organized 512-kword
×
8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35 µ m Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62W8512B is suitable for battery backup system.
Features
•
Single 3.3 V supply: 3.3 V ± 0.3 V
•
Access time: 55/70 ns (max)
•
Power dissipation
Active: 16.5 mW/MHz (typ)
Standby: 3.3 µW (typ)
•
Completely static memory. No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output: Three state output
•
Directly LV-TTL compatible: All inputs and outputs
•
Battery backup operation
HITACHI [ HITACHI SEMICONDUCTOR ]
