HMC624LP4 / 624LP4E
v09.0210
0.5 dB LSB GaAs MMIC 6-BIT
DIGITAL ATTENUATOR, DC - 6 GHz
Timing Diagram
(Latched Parallel Mode)
Parameter
Min. serial period, t
SCK
Control set-up time, t
CS
Control hold-time, t
CH
LE setup-time, t
LN
Min. LE pulse width, t
LEW
Min LE pulse spacing, t
LES
Serial clock hold-time from LE, t
CKN
Hold Time, t
PH.
Latch Enable Minimum Width, t
LEN
Setup Time, t
PS
Typ.
100 ns
20 ns
20 ns
10 ns
10 ns
630 ns
10 ns
0 ns
10 ns
2 ns
8
ATTENUATORS - DIGITAL - SMT
8-4
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
Note:
The parallel mode is enabled when P/S is set to low.
Direct Parallel Mode
- The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode
- The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
Power-Up States
If LE is set to logic LOW at power-up, the logic state of
PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines
the power-up state of the part per truth table. The
attenuator latches in the desired power-up state
approximately 200 ms after power-up.
PUP Truth Table
LE
0
0
0
0
1
PUP1
0
1
0
1
X
PUP2
0
0
1
1
X
Relative Attenuation
-31.5
-24
-16
Insertion Loss
0 to -31.5 dB
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Note: The logic state of D0 - D5 determines the
power-up state per truth table shown below when LE
is high at power-up.
Truth Table
Control Voltage Input
D5
High
D4
High
High
High
High
High
Low
High
Low
D3
High
High
High
High
Low
High
High
Low
D2
High
High
High
Low
High
High
High
Low
D1
High
High
Low
High
High
High
High
Low
D0
High
Low
High
High
High
High
High
Low
Reference
Insertion
Loss
0 dB
-0.5 dB
-1 dB
-2 dB
-4 dB
-8 dB
-16 dB
-31.5 dB
Bias Voltage
Vdd (V)
3
5
Idd (Typ.) (mA)
1.8
2.0
High
High
High
High
Control Voltage Table
State
Low
High
Vdd = +3V
0 to 0.5V @ <1 µA
2 to 3V @ <1 µA
Vdd = +5V
0 to 0.8V @ <1 µA
2 to 5V @ <1 µA
High
Low
Low
Any combination of the above states will provide an attenuation
equal to the sum of the bits selected.
For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
HITTITE [ HITTITE MICROWAVE CORPORATION ]
