HT23C020
A.C. test conditions
Output load: see figure right
Input rise and fall time: 10ns
Input pulse levels: 0.4V to 2.4V
Input and output timing reference levels:
0.8V and 2.0V (V
CC
=5V), 1.5V (V
CC
=3V)
Output load circuit
Functional Description
The HT23C020 has two modes, namely data
read mode and standby mode, controlled by
CE/CE/OE1/OE1,CE1/CE1/OE2/OE2/NC and
OE/OE/NC inputs.
•
Standby mode
•
Data read mode
The HT23C020 has lower current consumption,
controlled by the chip enable input (CE/CE and
CE1/CE1). When a low/high level is applied to
the CE/CE or CE1/CE1 input, regardless of the
output enable (OE/OE/NC) states, the chip will
enter the standby mode.
When both the chip enable (CE/CE/OE1/OE1,
CE1/CE1/OE2/OE2/NC) and the output en-
able (OE/OE/NC) are active, the chip is in
data read mode. Otherwise, active CE/CE,
CE1/CE1 and inactive OE/OE/NC result in
deselect mode. The output will remain in Hi-Z
state.
Timing Diagrams
•
Propagation delay due to address (CE/CE/OE1/OE1, CE1/CE1/OE2/OE2
and OE/OE are active)
•
Propagation delay due to chip and output enable (address valid)
5
21st Aug ’98
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
