HT46R01/HT46R02/HT46R03
Symbol
I
OH
R
PH
V
AD
E
AD
D
NL
I
NL
I
ADC
Parameter
I/O Port Source Current
Test Conditions
V
DD
3V
5V
3V
5V
¾
¾
¾
¾
3V
5V
8, 9 bit ADC
12 bit ADC, t
AD
=1ms
12 bit ADC, t
AD
=1ms
No load, t
AD
=1ms
Conditions
V
OH
=0.9V
DD
¾
¾
Min.
-2
-5
20
10
0
¾
¾
¾
¾
¾
Typ.
-4
-10
60
30
¾
±0.5
¾
±2.5
0.5
1.5
Max.
¾
¾
100
50
V
DD
±1
±2
±4
1
3
Unit
mA
mA
kW
kW
V
LSB
LSB
LSB
mA
mA
Pull-high Resistance
A/D Input Voltage
ADC Conversion Error
ADC Differential Non-linear
ADC Integral Non-linear
ADC Power Consumption
A.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
f
SYS1
System Clock
(Crystal OSC, RC OSC)
¾
¾
Conditions
2.2V~5.5V
3.3V~5.5V
4.5V~5.5V
Min.
400
400
400
Typ.
¾
¾
¾
Max.
4000
8000
12000
Ta=25°C
Unit
kHz
kHz
kHz
kHz
kHz
kHz
Hz
kHz
kHz
kHz
ms
ms
ms
t
SYS
ms
ms
mV
V/ms
ms
t
AD
t
AD
t
AD
t
AD
4.5V~
12MHz, Ta=25°C
5.5V
f
SYS2
System Clock
(Internal RC OSC)
(±5%)
3.3V~
8MHz, Ta=25°C
5.5V
2.7V~
4MHz, Ta=25°C
5.5V
f
SYS3
f
TIMER
System Clock (32768 Crystal)
¾
¾
Timer I/P Frequency (TMR)
¾
¾
t
WDTOSC
Watchdog Oscillator Period
t
RES
t
SST
t
INT
t
LVR
V
POR
R
POR
t
AD
t
ADC
t
ADS
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
Low Voltage Width to Reset
VDD Start Voltage to Ensure
Power-on Reset
VDD Rise Time to Ensure
Power-on Reset
ADC Clock Period
3V
5V
¾
¾
¾
¾
¾
¾
¾
8 bit ADC
ADC Conversion Time
¾
¾
9 bit ADC
12 bit ADC
ADC Sampling Time
¾
2.2V~5.5V
3.3V~5.5V
4.5V~5.5V
¾
¾
¾
Wake-up from Power Down
¾
¾
¾
¾
¾
¾
11400 12000 12600
7600
3800
¾
0
0
0
45
32
1
¾
1
0.25
¾
0.035
1
¾
¾
¾
¾
8000
4000
32768
¾
¾
¾
90
65
¾
1024
¾
1
¾
¾
¾
64
76
80
32
8400
4200
¾
4000
8000
12000
180
130
¾
¾
¾
2
100
¾
¾
¾
¾
¾
¾
Note: t
SYS
=1/f
SYS1
, 1/f
SYS2
or 1/f
SYS3
Rev. 1.00
5
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
