HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
Pin Description
Pin Name
PA0/AN0
Function
PA0
AN0
PA1
PA1/PFD/AN1
PFD
AN1
PA�½
PA�½/TC0/AN�½/VREF
TC0
AN�½
VREF
PA3
PA3/INTB/AN3
INTB
AN3
PA4
PA4/PWM0/TC1/AUD
PWM0
TC1
AUD
PA5
OSC�½
PA�½
OSC1
PA7
RES
PB0
SCOM0
PB1
SCOM1
PB�½
SCOM�½
PB3
SCOM3
PB4�½PB5
PB�½
SCSA
PB7
SCKA
PC0
AN4
PC1
AN5
PC�½
PWM�½
PC3
PWM1
PC4
XT�½
PC5
XT1
OPT
I/T
O/T
Descriptions
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
ANCSR0 AN
—
A/D channel 0
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
CTRL0
— CMOS PFD o�½tp�½t
ANCSR0 AN
—
A/D channel 1
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
—
ST
—
Exte�½nal Time�½ 0 clock inp�½t
ANCSR0 AN
—
A/D channel �½
ACSR
AN
—
ADC �½efe�½ence inp�½t
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
—
ST
—
Exte�½nal Inte�½�½�½pt inp�½t
ANCSR0 AN
—
A/D channel 3
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
CTRL0
— CMOS PWM o�½tp�½t
—
ST
—
Exte�½nal Time�½ 1 clock inp�½t
—
—
AN
DAC o�½tp�½t
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
CO
—
OSC Oscillato�½ pin
PAPU
Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p and
ST CMOS
PAWK
wake-�½p.
CO
OSC
—
Oscillato�½ pin
PAWK
ST NMOS Gene�½al p�½�½pose I/O. Registe�½ enabled wake-�½p.
CO
ST
—
Reset inp�½t
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
SCOMC
— SCOM Softwa�½e cont�½olled 1/�½ bias LCD COM
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
SCOMC
— SCOM Softwa�½e cont�½olled 1/�½ bias LCD COM
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
SCOMC
— SCOM Softwa�½e cont�½olled 1/�½ bias LCD COM
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
SCOMC
— SCOM Softwa�½e cont�½olled 1/�½ bias LCD COM
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
—
ST
—
SPI Slave Select
PBPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p
—
ST CMOS SPI Se�½ial Clock
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
ANCSR0 AN
—
A/D channel 4
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
ANCSR0 AN
—
A/D channel 5
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
CTRL�½
— CMOS PWM o�½tp�½t
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
CTRL0
— CMOS PWM o�½tp�½t
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
CO
—
LXT Low f�½eq�½enc�½ c�½�½stal pin
PCPU
ST CMOS Gene�½al p�½�½pose I/O. Registe�½ enabled p�½ll-�½p.
CO
—
LXT Low f�½eq�½enc�½ c�½�½stal pin
PA5/OSC�½
PA�½/OSC1
PA7/RES
PB0/SCOM0
PB1/SCOM1
PB�½/SCOM�½
PB3/SCOM3
PB4�½PB5
PB�½/SCSA
PB7/SCKA
PC0/AN4
PC1/AN5
PC�½/PWM�½
PC3/PWM1
PC4/XT�½
PC5/XT1
Rev. 1.00
5
�½an�½a�½�½ �½�½�½ �½011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
