HT48R10A-1/HT48C10-1
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The RTC oscillator is still running in the HALT mode (If
the RTC oscillator is enabled).
Reset
There are three ways in which a reset can occur:
·
RES reset during normal operation
·
RES reset during HALT
·
WDT time-out reset during normal operation
1 0 k
W
0 .1
m
F *
V D D
R E S
S S T T im e - o u t
C h ip
R e s e t
t
S
S T
Reset Timing Chart
V
D D
0 .0 1
m
F *
1 0 0 k
W
R E S
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a
²warm
re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the
²initial
condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip
resets².
TO PDF
0
u
0
1
1
0
u
1
u
1
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Reset Circuit
Note:
²*²
Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
W a rm
R e s e t
H A L T
W D T
R E S
O S C 1
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
C o ld
R e s e t
Reset Configuration
Note:
²u²
means
²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer/Event Counter
Input/Output Ports
SP
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
Rev. 1.90
12
November 4, 2005
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
