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HT48R31 参数 Datasheet PDF下载

HT48R31图片预览
型号: HT48R31
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器系列 [8-Bit Microcontroller Series]
分类和应用: 微控制器
文件页数/大小: 59 页 / 2624 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT48CXX/HT48RXX
Pin Description of HT48C70
Pin Name
I/O
Mask
Option
Wake-up
Pull-high
or None
Pull-high
or None
Pull-high
or None
Crystal or
RC
Pull-high
or None
Pull-high
or None
Pull-high
or None
Pull-high
or None
Function
Bidirectional 8-bit input/output ports
Each bit can be configured as a wake-up input by mask option.
Software instructions determine the CMOS output or schmitt
trigger input with or without pull high resistor (by mask option).
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
Negative power supply, GND
External interrupt schmitt trigger with pull high resistor
Edge trigger is activated during high to low transition.
Schmitt trigger input for timer/event counter 0
Schmitt trigger input for timer/event counter 1
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
Schmitt trigger reset input, active low
Positive power supply
OSC1 and OSC2 are connected to an RC network or a crystal
(by mask option) for the internal system clock. In the case of RC
operation, OSC2 is the output terminal for 1/4 system clock.
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
Bidirectional 8-bit input/output ports
Software instructions determine the CMOS output or schmitt
trigger input (pull-high depends on mask option).
PA0~PA7
I/O
PB0~PB7
VSS
INT
TMR0
TMR1
PC0~PC7
RES
VDD
OSC1
OSC2
I/O
I
I
I
I/O
I
I
O
PD0~PD7
I/O
PE0~PE7
I/O
PF0~PF7
I/O
PG0~PG7
I/O
9
25th May ’99