HT48RU80/HT48CU80
Higher-order byte register (TBLH) is read only. The ta-
ble pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in the TBLP.
The TBLH is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service Routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words, using the table read instruc-
tion in the main routine and the ISR simultaneously
should be avoided. However, if the table read instruc-
tion has to be applied in both the main routine and the
ISR, the interrupt should be disabled prior to the table
read instruction. It will not be enabled until the TBLH
has been backed up. All table related instructions re-
quire two cycles to complete the operation. These ar-
eas may function as normal program memory
depending upon the requirements.
Stack Register
-
STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 16 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a
²CALL²
is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 16 return ad-
dresses are stored).
Data Memory
-
RAM
The data memory (RAM) is designed with 617´8 bits,
and is divided into two functional groups, namely, spe-
cial function registers and general purpose data mem-
ory (192´8bits´3banks), most of which are readable/
writeable, although some are read only.
[BP REG] Bit1~Bit0
00
01
10
RAM Bank
0
1
2
The special function registers consist of an Indirect ad-
dressing register 0 (IAR0;00H), a Memory pointer regis-
ter 0 (MP0;01H), an Indirect addressing register 1
(IAR1;02H), a Memory pointer register 1 (MP1;03H), a
Bank pointer (BP;04H), an Accumulator (ACC;05H), a
Program counter lower-order byte register (PCL;06H), a
lower-order byte table pointer (TBLP;07H), a Table
higher-order byte register (TBLH;08H), a Watchdog
Timer option setting register (WDTS;09H), a Status reg-
ister (STATUS;0AH), an Interrupt control register 0
(INTC0;0BH), a Timer/Event Counter 0 higher order
byte register (TMR0H;0CH), a Timer/Event Counter 0
lower order byte register (TMR0L;0DH), a Timer/Event
Counter 0 control register (TMR0C;0EH), a Timer/Event
Counter 1 higher order byte register (TMR1H;0FH), a
Timer/Event Counter 1 lower order byte register
(TMR1L;10H), a Timer/Event Counter 1 control register
(TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H,
PD;18H, PE;1AH, PF;1CH, PG;25H) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H,
PEC;1BH, PFC;1DH, PGC;26H), a Timer/Event Coun-
ter 2 (TMR2;21H), a Timer/Event Counter 2 control reg-
ister (TMR2C;22H), a higher-order byte table pointer
( T BH P; 1 F H ) , a n I nt er r up t co nt r ol r eg i st e r 1
(INTC1;1EH), a UART Status register (USR;28H), a
UART Control register 1 (UCR1;29H), a UART Control
register 2 (UCR2;2AH), a UART TX/RX Buffer register
(TXR/RXR;2BH), and a UART Baud Rate generator
prescaler register (BRG;2CH). On the other hand, the
general purpose data memory, addressed from 40H to
FFH (bank0~2), is used for data and control information
under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by
²SET
[m].i² and
²CLR
[m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result 00H. Writing indirectly results
in no operation. The memory pointer registers (MP0 and
MP1) are 8-bit registers.
Accumulator
-
ACC
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Rev. 1.00
9
April 12, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
