HT604L/HT614/HT692
Block Diagram
O S C 2
O S C 1
O s c illa to r
D iv id e r
D a ta S h ift
R e g is te r
L a tc h C ir c u it
D a ta
D IN
B u ffe r
D a ta D e te c to r
S y n c . D e te c to r
C o m p a ra to r
C o m p a ra to r
C o n tr o l L o g ic
T r a n s m is s io n G a te C ir c u it
B u ffe r
V T
A d d re s s
V D D
V S S
Note:
The address/data pins are available in various combinations (refer to the address/data table).
Pin Assignment
Latch Series
Momentary Series
1 0 -A d d re s s
4 -D a ta
A 1 1
D 1 2
D 1 3
D 1 4
D 1 5
V T
6
7
8
9
1 0
D IN
O S C 2
O S C 1
V S S
5
4
3
2
1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
V D D
A 9
A 8
A 7
A 6
A 4
A 3
A 2
A 1
A 0
1 0 -A d d re s s
4 -D a ta
A 1 1
D 1 2
D 1 3
D 1 4
D 1 5
V T
6
7
8
9
1 0
D IN
O S C 2
O S C 1
V S S
5
4
3
2
1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
V D D
A 9
A 8
A 7
A 6
A 4
A 3
A 2
A 1
A 0
1 0 -A d d re s s
2 -D a ta
A 1 1
A 1 2
D 1 4
D 1 5
4
5
6
7
8
9
V T
D IN
O S C 2
O S C 1
V S S
3
2
1
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
V D D
A 9
A 8
A 7
A 6
A 3
A 2
A 1
A 0
H T 6 0 4 L
2 0 D IP -A /S O P -A
H T 6 1 4
2 0 D IP -A /S O P -A
H T 6 9 2
1 8 D IP -A
Pin Description
Pin Name
A0~A12
D10~D17
DIN
VT
OSC1
OSC2
VSS
VDD
I/O
I
O
I
O
I
O
¾
¾
Internal
Connection
TRANSMISSION
GATE
CMOS OUT
CMOS IN
CMOS OUT
OSCILLATOR
OSCILLATOR
¾
¾
Description
Input pins for address A0~A12 setting
They can be externally set to VDD, VSS or left open.
Output data pins
Serial data input pin
Valid transmission, active high
Oscillator input pin
Oscillator output pin
Negative power supply, ground
Positive power supply
Rev. 1.10
2
January 24, 2003
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
