HT7612/HT7612B
LVD & CDS Detecting Circuit
The external and internal detecting circuits for LVD and
CDS are shown in Fig.13. When the input voltage V
LVD
is lower than 1.1V, the comparator outputs a low level
which means that V
DD
is lower than the minimum oper-
ating voltage (Vmin). When V
CDS
is lower than V
L
, the
comparator outputs a high level which means that it is
daytime, otherwise it is night.
Where
V
L V D
V
D D
V
R
X
R E F
R
Y
B U Z /L V D
B U Z /C D S
R
T E S T /S C
L V D
R
C D S
Fig.13 External Application Circuit
=
R
R
L V D
L V D
+
R
X
C D S
V
D D
Note:
V
C D S
=
R
R
C D S
+
R
Y
V
R E F
When the CDS input voltage is lower than V
L
, it
means that a daytime condition exists for the
PIR circuit.
Relationship LVD and CDS
The LVD and CDS trigger timing are shown in Fig.14 and Fig.15 respectively. In Fig.14, When an LVD condition occurs,
the LED will flicker and the buzzer will emit a tone. In Fig.15, When the CDS state changes from low to high, the output
of the PIR is enabled after 10 sec for the HT7612 or 0 sec for the HT7612B, and when the CDS sate changes from high
to low, will be disabled.
Fig.14 Trigger Timing of LVD
CDS State
(Internal signal)
10 sec for HT7612
0 sec for HT7612B
+ Trigger
Level
Output
Enable
Comparator
Input
Comparator
Output
- Trigger
Level
Fig.15 Trigger Timing of CDS
Rev. 1.50
8
February 21, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
