HT82A851R
Functional Description
Execution Flow
The microcontroller system clock is sourced from a
crystal oscillator. The system clock is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while
decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each
instruction to be effectively executed in a cycle. If an
instruction changes the program counter, two cycles are
required to complete the instruction.
Program Counter
-
PC
The program counter, PC, controls the sequence in
which the instructions stored in the program memory are
executed. Its contents specify the full program memory
range.
After accessing a program memory word to fetch an
instruction code, the contents of the program counter
are incremented by one. The program counter then
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
points to the memory word containing the next
instruction code.
When executing a jump instruction, a conditional skip
execution, loading to the PCL register, performing a
subroutine call or returning from a subroutine, an initial
reset, an internal interrupt, external interrupt or return
from interrupts, the PC manipulates the program
transfer by loading the address corresponding to each
instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the next instruction is executed.
The lower byte of the program counter, PCL, is a
readable and writeable register. Moving data into the
PCL performs a short jump. The destination will be
within the current program memory page.
When a control transfer takes place, an additional
dummy cycle is required.
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Initial Reset
Reserved
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Play Interrupt
Serial Interface Interrupt
Record Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter
*11
0
0
0
0
0
0
0
*11
#11
S11
*10
0
0
0
0
0
0
0
*10
#10
S10
*9
0
0
0
0
0
0
0
*9
#9
S9
*8
0
0
0
0
0
0
0
*8
#8
S8
*7
0
0
0
0
0
0
0
@7
#7
S7
*6
0
0
0
0
0
0
0
@6
#6
S6
*5
0
0
0
0
0
0
0
@5
#5
S5
*4
0
0
0
0
1
1
1
@4
#4
S4
*3
0
0
1
1
0
0
1
@3
#3
S3
*2
0
1
0
1
0
1
0
@2
#2
S2
*1
0
0
0
0
0
0
0
@1
#1
S1
*0
0
0
0
0
0
0
0
@0
#0
S0
Program Counter+2
Program Counter
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.20
5
S11~S0: Stack register bits
@7~@0: PCL bits
June 15, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
