HI-3282
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1mhz +0.1% with 60/40 duty cycle
PARAMETER
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
Spacing - PL1 or PL2
Delay - PL2 HIGH to TX/R LOW
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - ENTX HIGH to 429DO or 429D0: High Speed
Delay - ENTX HIGH to 429DO or 429D0: Low Speed
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX L0W
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
Hold - PL HIGH to EN HIGH
Delay - TX/R LOW to ENTX HIGH
Master Reset Pulse Width
ARINC Data Rate and Bit Timing
t
ENPL
t
PLEN
t
TX/REN
t
MR
0
0
0
50
± 1%
ns
ns
ns
ns
t
PL2EN
t
ENDAT
t
ENDAT
t
DTX/R
t
ENTX/R
0
0
25
200
50
µs
µs
µs
ns
ns
t
PL
t
DWSET
t
DWHLD
t
PL12
t
TX/R
50
50
10
0
840
ns
ns
ns
ns
ns
t
D/R
t
D/R
t
D/REN
t
END/R
t
SELEN
t
ENSEL
t
ENDATA
t
DATAEN
t
EN
t
ENEN
80
50
0
200
0
0
50
50
80
30
16
128
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
t
CWSTR
t
CWSET
t
CWHLD
50
50
0
ns
ns
ns
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
HOLT INTEGRATED CIRCUITS
9
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
