HI-8282A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
DATA
BUS
PIN
BDO5
FUNCTION CONTROL
DESCRIPTION
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
CLK is divided either by 10 or
80 to obtain XMTR data clock
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC
BIT
SELF TEST
0 = ENABLE
BYTE 2
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO6
RECEIVER 1
DECODER
1 = ENABLE
BDO7
-
-
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
BDO8
-
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
BD10
-
-
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BD11
-
-
The HI-8282A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13v signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BD12
INVERT
XMTR
PARITY
XMTR DATA
CLK SELECT
RCVR DTA
CLK SELECT
1 = ENABLE
BD13
0 = ÷10
1 = ÷80
0 = ÷10
1 = ÷80
HI-8282A-10
The HI-8282A-10 option is similar to the HI-8282A with the exception
that it allows an external 10 Kohm resistor to be added in series with
each ARINC input without affecting the ARINC input thresholds. This
option is especially useful in applications where lightning protection
circuitry is also required.
Each side of the ARINC bus must be connected through a 10 Kohm
series resistor in order for the chip to detect the correct ARINC levels.
The typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so that
with the external 10 Kohm resistors, they are just below the standard
6.5 V minimum ARINC data threshold and just above the 2.5 V
maximum ARINC null threshold.
The receivers of the HI-8282A-10 when used with external
10 Kohm resistors will withstand DO-160D, Level 3, waveforms 3,
4 and 5A. No additional lightning protection circuit is necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
BD14
v
cc
429DI1(A)
OR
429DI2(A)
GND
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
NULL
v
cc
429DI1(B)
OR
429DI2(B)
ZEROES
GND
FIGURE 1. ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
