HI-8282A
AC ELECTRICAL CHARACTERISTICS
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1ꢀ with 60/40 duty cycle
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
130
130
0
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
ns
ns
200
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
tSELEN
tENSEL
20
20
ns
ns
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
200
30
ns
ns
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tEN
tENEN
200
50
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
tPL
200
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
110
10
ns
ns
Spacing - PL1 or PL2
tPL12
tTX/R
0
ns
ns
Delay - PL2 HIGH to TX/R LOW
840
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
0
µs
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed
Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed
tENDAT
tENDAT
25
200
µs
µs
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
400
ns
ns
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
Hold - PL HIGH to EN HIGH
tENPL
tPLEN
tTX/REN
tMR
0
0
ns
ns
ns
ns
Delay - TX/R LOW to ENTX HIGH
0
Master Reset Pulse Width
200
ARINC Data Rate and Bit Timing
1ꢀ
HOLT INTEGRATED CIRCUITS
9
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
