HI-8382, HI-8383
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input. Each logic
input, including the power enable (STROBE) input, are
TTL/CMOS compatible. Besides reducing chip current drain,
STROBE also floats each output. However the overvoltage
fuses and diodes of the HI-8382 are not switched out.
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-8382;
typically +15V, -15V and +5V. The chip also works with ±12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2V
REF
. If a value of
V
REF
other than +5V is needed, a separate +5V power supply
is required for pin V
1
.
With the DATA (A) input at a logic high and DATA (B) input at a
logic low, A
OUT
will switch to the +V
REF
rail and B
OUT
will
switch to the -V
REF
rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULL state).
The driver output impedance, R
OUT
, is nominally 75 ohms.
The rise and fall times of the outputs can be calibrated through
the selection of two external capacitor values that are
connected to the C
A
and C
B
input pins. Typical values for
high-speed operation (100KBPS) are C
A
= C
B
= 75pF and for
low-speed operation (12.5 to 14KBPS) C
A
= C
B
= 500pF.
The driver can be externally powered down by applying a logic
high to the STROBE input pin. If this feature is not being used,
the pin should be tied to ground.
The C
A
and C
B
pins are inputs to unity gain amplifiers.
Therefore they must be allowed to swing to -5V. Provision to
V
REF
+V
C
A
switch capacitors must be done with analog switches that
allow voltages below their ground.
Both ARINC outputs of the HI-8382 are protected by internal
fuses capable of sinking between 800 - 900 mA for short
periods of time (125µs).
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The recom-
mended sequence is +V followed by V
1
, always ensuring that
+V is the most positive supply. The -V supply is not critical
and can be asserted at any time.
+5V
+15V
V
REF
DATA (A)
V1
SYNC
CLOCK
A
OUT
+V
INPUTS
DATA (B)
CA
CB
STROBE
GND
-V
TO ARINC BUS
B
OUT
-15V
Figure 1.
ARINC 429 BUS APPLICATION
A
OUT
DATA (A)
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
CLOCK
R
OUT
/ 2
OUTPUT
DRIVER (A)
R
L
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
C
L
F
A
R
OUT
/ 2
OUTPUT
DRIVER (B)
F
B
DATA (B)
V
1
STROBE
CURRENT
REGULATOR
Not included on HI-8383
OVER VOLTAGE
CLAMPS
GND
-V
C
B
B
OUT
Figure 2.
FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
