HI-8570, HI-8571
PACKAGE THERMAL CHARACTERISTICS
Maximum ARINC Load
PACKAGE STYLE
1
ARINC 429
DATA RATE
Low Speed
3
High Speed
4
SUPPLY CURRENT (mA)
Ta = 25
°
C
Ta = 85
°
C
2
JUNCTION TEMP, Tj
°
C
Ta = 25
°
C
Ta = 85
°
C
Ta = 125
°
C
Ta = 125
°
C
8 Lead Plastic ESOIC
5
20.98
26.40
20.96
26.16
20.96
25.96
38.24
44.78
98.34
104.66
138.92
144.59
TXAOUT and TXBOUT Shorted to Ground
PACKAGE STYLE
1
6,7,8
ARINC 429
DATA RATE
Low Speed
3
SUPPLY CURRENT (mA)
Ta = 25
°
C
Ta = 85
°
C
2
JUNCTION TEMP, Tj
°
C
Ta = 25
°
C
Ta = 85
°
C
Ta = 125
°
C
Ta = 125
°
C
8 Lead Plastic ESOIC
5
30.26
30.44
29.22
29.42
28.46
28.68
53.75
53.92
112.76
112.95
152.04
152.25
High Speed
4
Notes:
1. All data taken in still air.
2. At 100% duty cycle, 5V power supplies.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
5. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered.
6. Similar results would be obtained with TXAOUT shorted to TXBOUT.
7. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
8. Data will vary depending on air flow and the method of heat sinking employed.
HEAT SINK - ESOIC PACKAGES
An 8-pin thermally enhanced SOIC package is used for the
HI-8570/HI-8571 products. The ESOIC package includes
a metal heat sink located on the bottom surface of the
device. This heat sink should be soldered down to the
printed circuit board for optimum thermal dissipation. The
heat sink is electrically isolated from the chip and can be
soldered to any ground or power plane. However, since
the chip’s substrate is at V+, connecting the heat sink to
this power plane is recommended to avoid coupling noise
into the circuit.
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
