HI-8581, HI-8589
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
Both the HI-8581and HI-8589 contain 10 data flip flops whose
D inputs are connected to the data bus and clocks connected to
CWSTR. Each flip flop provides options to the user as follows:
DATA
BUS
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
BYTE 1
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
9
31 30 32
1
2
3
4
5
6
7
8
DATA
BUS
PIN
BDO5
FUNCTION CONTROL
DESCRIPTION
If enabled, the transmitter’s digital
outputs are internally connected
to the receiver logic inputs
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
If enabled, ARINC bits 9 and
10 must match the next two
Control word bits
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
CLK is divided either by 10 or
80 to obtain XMTR data clock
CLK is divided either by 10 or
80 to obtain RCVR data clock
ARINC
BIT
SELF TEST
0 = ENABLE
BYTE 2
DATA
BUS
ARINC
BIT
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
BDO6
RECEIVER 1
DECODER
1 = ENABLE
BDO7
-
-
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
BDO8
-
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
BD10
-
-
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BD11
-
-
BD12
INVERT
XMTR
PARITY
XMTR DATA
CLK SELECT
RCVR DTA
CLK SELECT
1 = ENABLE
The HI-8581 and HI-8589 guarantee recognition of these levels with
a common mode Voltage with respect to GND less than ±4V for the
worst case condition (4.75V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
BD13
0 = ÷10
1 = ÷80
0 = ÷10
1 = ÷80
BD14
v
cc
429DI1 (A)
OR
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
429DI2 (A)
GND
NULL
v
cc
429DI1 (B)
OR
ZEROES
429DI2 (B)
GND
FIGURE 1.
ARINC RECEIVER INPUT
HOLT INTEGRATED CIRCUITS
3
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
