HI-8581, HI-8589
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
SELF TEST
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
BIT BD12
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either TXA(OUT) or TXB(OUT). The 31 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
31 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
LINE DRIVER
TXA(OUT)
TXB(OUT)
WORD CLOCK
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
8 X 31 FIFO
ADDRESS
LOAD
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
TX/R
ENTX
FIFO
LOADING
SEQUENCER
PL1
PL2
DATA BUS
DATA
CLOCK
DATA CLOCK
DIVIDER
CLK
TX CLK
FIGURE 3.
TRANSMITTER BLOCK DIAGRAM
CONTROL BIT
BD13
HOLT INTEGRATED CIRCUITS
5
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
