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HI-8582CJI-10 参数 Datasheet PDF下载

HI-8582CJI-10图片预览
型号: HI-8582CJI-10
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC 429片上系统 [ARINC 429 System on a Chip]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路数据传输时钟
文件页数/大小: 16 页 / 236 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-8582, HI-8583
June 2013
ARINC 429
System on a Chip
FEATURES
ARINC specification 429 compatible
Dual receiver and transmitter interface
Analog line driver and receivers connect
directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for
transmitter and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
GENERAL DESCRIPTION
The HI-8582/HI-8583 from Holt Integrated Circuits are a
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-8582/HI-8583 design offers many enhancements to the
industry standard HI-8282 architecture. The device
provides two receivers each with label recognition, 32 by
32 FIFO, and analog line receiver. Up to 16 labels may be
programmed for each receiver. The independent transmit-
ter has a 32 X 32 FIFO and a built-in line driver. The status
of all three FIFOs can be monitored using the external
status pins, or by polling the HI-8582/HI-8583 status
register. Other new features include a programmable
option of data or parity in the 32nd bit, and the ability to
unscramble the 32 bit word. Also, versions are available
with different values of input resistance and output
resistance to allow users to more easily add external
lightning protection circuitry. The device can be used at
nonstandard data rates when an option pin, NFD, is
invoked.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-8582/HI-8583 apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
PIN CONFIGURATION
(Top View)
52 - D/R1
51 - RIN2B
50 - RIN2A
49 - RIN1B
48 - RIN1A
47 - VDD
46 - N/C
45 - TEST
44 - MR
43 - TXCLK
42 - CLK
41 - RSR
40 - N/C
APPLICATIONS
Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-8582PQI
HI-8582PQT
&
HI-8583PQI
HI-8583PQT
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(See page 14 for additional pin configuration)
(DS8582 Rev. O)
HOLT INTEGRATED CIRCUITS
www.holtic.com
BD10 - 14
BD09 - 15
BD08 - 16
BD07 - 17
BD06 - 18
N/C - 19
GND - 20
NFD - 21
BD05 - 22
BD04 - 23
BD03 - 24
BD02 - 25
BD01 - 26
06/13