HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
ONE
S
Q
LATCH
R
TEST
ROUTA
TEST
TESTA
TESTA
'
TESTB
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
NULL
TEST
ZERO
S
Q
LATCH
R
ROUTB
TEST
TESTB
TESTA
'
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
HARDWIRE
OR
DRIVE FROM LOGIC
{
2
8
4
VCC
TESTA
TESTB
ROUTA
ROUTB
6
7
RXD1
RXD0
HI-8588
RINA
RINB
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8588 interfacing an ARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
ARINC
Channel
3
HI-6010
5
15V
1
6
SLP1.5
TXAOUT
V+
TX1IN
8 BIT BUS
8
3
2
TXD1
ARINC
Channel
7
HI-8586
TXBOUT
GND
V-
TX0IN
TXD0
4
5
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
