HI-8783, HI-8784, HI-8785
PIN DESCRIPTIONS
PIN
PIN
PIN
HI-8783 HI-8783 HI-8784
(20-pin) (22-pin) HI-8785
1
2
3-10
11
12
-
13
14
15
16
17
-
18
19
-
-
20
-
22
1
2-8,10
11
12
-
14
15
16
17
18
-
19
20
-
-
21
-
1
2
3-9,11
12
13
14
15
16
17
18
19
20
-
-
21
22
23
24
SYMBOL
FUNCTION
DESCRIPTION
VCC
561 SYNC
Dn
GND
A0
SLP1.5
WRITE
RESET
XMIT CLK
XMT RDY
V-
DATA ONE
TXAOUT
TXBOUT
561 DATA
V+
power supply +5 volt rail,
digital output
digital inputs
digital input
digital input
digital input
digital input
digital input
digital output
ARINC 561 Sync signal
Parallel 8 bit Data Input
Byte address, A0=1 for 1st byte, A0=0 for 2nd, 3rd & 4th bytes
Selects the slope of the line driver. High = 1.5us
Write strobe, loads data on rising edge
Registers and sequencing logic initialized when low
Clock input for the transmitter
Goes high if the buffer register is empty
When high the 32nd bit output is odd parity
Goes high for each ARINC bit output that is a “one”
Goes high for each ARINC bit output that is a “zero”
power supply Ground
PARITY ENB digital input
digital output
power supply -10 volt rail
DATA ZERO digital output
analog output Line driver ouptut - A side
analog output Line driver output - B side
digital output
Serial output for ARINC 561 data
power supply +10 volt rail
FUNCTIONAL DESCRIPTION
The HI-8783 is a parallel to serial converter, which when
loaded with four eight bit parallel bytes, outputs the data as a
32 bit serial word. Timing circuitry inserts a 4 bit gap at the
end of each 32 bit word. An input buffer register allows load
operations to take place while the previously loaded word is
being transmitted.
If the PARITY ENB pin is high, the 32nd bit will be a parity bit,
inserted so as to make the 32 bit word have odd parity. If the
PARITY ENB pin is low, the 32nd bit will be the D7 bit of the
4th byte.
Outputs are provided for both ARINC 429/575 (DATA ONE
and DATA ZERO pins) and ARINC 561 (561 DATA and 561
SYNC pins) type data.
A low signal applied to the RESET pin resets the HI-8783’s
internal logic so that spurious transmission does not take
place during power-up. The registers are cleared so that a
continuous gap will be transmitted until the first word is
loaded into the transmitter.
Input data can be loaded when the XMT RDY signal is high,
which indicates the input buffer register is empty. The first 8
bit byte is the label byte and is loaded with the A0 input high,
which initializes the internal byte counter. The remaining
three bytes are loaded with A0 in the low state. Once A0 is
set low, it must not go high until after the fourth byte is loaded.
Each 8 bit byte is loaded into the input buffer register by a low
pulse on the WRITE input. After the fourth byte is loaded, the
XMT RDY output goes low.
The contents of the input buffer register are transferred to the
output register during the fourth bit period of the gap. If the
fourth gap bit period of the previous word has already been
transmitted, the contents of the input buffer register will be
transferred to the output shift register during the first bit pe-
riod after the loading of the fourth byte, and the XMT RDY out-
put goes high.
After the output shift register is loaded, the data is shifted out
to the output logic in the order shown in figure 2.
The 561 SYNC output pulses low when the XMT CLK is low
during the 8th bit of the ARINC transmission.
The XMIT CLK is the same as the data rate.
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
