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HRF-AT4521-TR 参数 Datasheet PDF下载

HRF-AT4521-TR图片预览
型号: HRF-AT4521-TR
PDF下载: 下载PDF文件 查看货源
内容描述: 31.0分贝, DC - 4GHz的, 5位串行数字衰减器 [31.0 dB, DC-4GHz, 5 Bit Serial Digital Attenuator]
分类和应用: 衰减器
文件页数/大小: 8 页 / 92 K
品牌: HONEYWELL [ HONEYWELL SOLID STATE ELECTRONICS CENTER ]
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HRF-AT4521
Preliminary
31.0 dB, DC-4GHz, 5 Bit
Serial Digital Attenuator
Features
Very Low DC Power Consumption
Attenuation In Steps From 1 dB To 31 dB
Single Or Dual Power Supply Voltages
Serial Data Interface
50 Ohm Compatible Impedance
TM
Space Saving LPCC Surface Mount Packaging
Product Description
The Honeywell HRF-AT4521 is a 5-bit digital
attenuator that is ideal for use in broadband
communication system applications that require
accuracy, speed and low power consumption. The
HRF-AT4521 is manufactured with Honeywell's
patented Silicon On Insulator (SOI) CMOS
manufacturing
technology, which provides the
performance of GaAs with the economy and
integration capabilities of conventional CMOS.
HRF-AT4521 in LPCC™ Package
RF Electrical Specifications @ + 25
o
C
Parameter
Insertion Loss
Test Condition
Frequency
DC – 0.5 GHz
2.0 GHz
3.0 GHz
4.0 GHz
DC – 2.0 GHz
DC – 2.0 GHz
Minimum
Typical
1.8
2.8
--
--
24
29
Maximum
Units
dB
dB
dB
dB
dBm
dBm
1dB Compression
1dB Compression
Input IP3
VSS = 0V, Input Power
VSS = - VDD, Input Power
VSS = 0V Two-tone inputs
DC – 2.0 GHz
38
dBm
Up To +5 dBm @ 0 dBm
Attenuation
Input IP3
V
ss
= - V
DD
DC – 2.0 GHz
>38
dBm
Two-tone inputs Up To + 5
dBm @ 0 dBm Attenuation
Return Loss*
Any Combination of Bits
DC - 4.0 GHz
11
dB
Attenuation Accuracy
All attenuation states
DC – 1.0 GHz
+/-(0.3 + 3% of programmed IL)
dB
All attenuation states
2.0 GHz
+/-(0.3 + 3% of programmed IL)
dB
All attenuation states
3.0 GHz
+/-(0.4 + 4% of programmed IL)
dB
All attenuation states
4.0 GHz
+/-(0.5 + 6% of programmed IL)
dB
Trise, Tfall*
10% To 90%
TBD
nS
Ton, Toff (Tpd)
50% Cntl To 90%/10%RF
nS
Transients
In-Band
mV
T clock Period (Tprd)*
T high / T low = �½ minimum clock period
50
nS
T data set up (Tsup)*
Set up to rising edge of clock
5
nS
T data hold (Thld)*
Data hold after rising edge of clock
2
nS
T latch set up (Tlsup)*
Data set up to falling edge of OE
5
nS
0.01uF Decoupling Capacitors Required On Power Supply Rails.
________________________________________________________________________________________________________
*By design
Web Site:
www.mysoiservices.com
Honeywell
Email:
mysoiservices@honeywell.com
Solid State Electronics Center
12001 State Highway 55
2002 4521W
Published June 2002 Page 1
Plymouth, Minnesota 55441-4799
1-800-323-8295