7
Switching Specifications (R
L
= Internal Pull-up)
Over recommended operating conditions:
(T
A
= -55°C to +125°C, V
CC
= +4.5 V to 30 V, I
F(ON)
= 10 mA to 20 mA, V
F(OFF)
= -5 V to 0.8 V) unless
otherwise specified.
Parameter
Propagation
Delay Time to
Low Output
Level
Propagation
Delay Time to
High Output
Level
Pulse Width
Distortion
Propagation
Delay
Difference
Between Any
Two Parts
Output High
Level Common
Mode Transient
Immunity
Output Low
Level Common
Mode Transient
Immunity
Power Supply
Rejection
Group A
Symbol Subgrps.
[12]
Min. Typ.* Max. Units
t
PHL
9, 10, 11
20
185
500
ns
Test Conditions
I
F(on)
= 10 mA,
V
F(off)
= 0.8 V,
V
CC
= 15.0 V,
C
L
= 100 pF,
V
THLH
= 2.0 V
V
THHL
= 1.5 V
Fig.
5, 8,
Note
3, 4,
5, 6,
7
t
PLH
9, 10, 11
220
415
750
ns
PWD
t
PLH
-
t
PHL
9, 10, 11
9, 10, 11
150
-225 150
600
650
ns
ns
11
8
|CM
H
|
10
kV/µs
I
F
= 0 mA, V
CC
= 15.0 V,
V
O
> 3.0 V C
L
= 100 pF,
V
CM
= 1000
T
A
= 25°C
I
F
= 16 mA
V
O
< 1.0 V
6, 21
9
|CM
L
|
10
kV/µs
10
PSR
1.0
V
P-P
Square Wave, t
RISE
, t
FALL
> 5 ns, no bypass
capacitors.
7
*All typical values at 25°C, V
CC
= 15 V.
Notes:
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I
O
) to the forward LED input current
(I
F
) times 100.
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 kΩ resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can
be improved by using an external 20 kΩ 1% load resistor. For more information on how propagation delay varies with load
resistance, see Figure 8.
6. The R
L
= 20 kΩ, C
L
= 100 pF represents a typical IPM (Intelligent Power Module) load.
7. Use of a 0.1
µF
bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in t
PLH
and t
PHL
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specifications section.)
9. Common mode transient immunity in a Logic High level is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to
assure that the output will remain in a Logic High state (i.e., V
O
> 3.0 V).
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to
assure that the output will remain in a Logic Low state (i.e., V
O
< 1.0 V).
11. Pulse Width Distortion (PWD) is defined as the difference between t
PLH
and t
PHL
for any given device.
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25°C, +125°C,
and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11 respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
HP [ AGILENT(HEWLETT-PACKARD) ]
