7
Electrical Description
Pin Function
Chip Enable (CE
1
and CE
2
, pins
3 and 4)
Clear
(CLR, pin 5)
Cursor Enable
(CUE pin 11)
Cursor Select
(CU, pin 10)
Description
CE
1
and CE
2
must be a logic 0 to write to the
display.
When CLR is a logic 0 the ASCII RAM is reset
to 20hex (space) and the Control Register/
Attribute RAM is reset to 00hex.
CUE determines whether the IC displays the
ASCII or the Cursor memory. (1 = Cursor,
0 = ASCII.)
CU determines whether data is stored in the
ASCII RAM or the Attribute RAM/Control
Register. (1 = ASCII, 0 = Attribute RAM/
Control Register.)
WR must be a logic 0 to store data in the
display.
A
0
-A
1
selects a specific location in the display
memory. Address 00 accesses the far right
display location. Address 11 accesses the far
left location.
D
0
-D
6
are used to specify the input data for
the display.
V
DD
is the positive power supply input.
GND is the display ground.
BL is used to flash the display, blank the
display or to dim the display.
Display Internal Block
Diagram
Figure 1 shows the HDLX-3416
display internal block diagram.
The CMOS IC consists of a 4 x 7
Character RAM, a 2 x 4 Attribute
RAM, a 5 bit Control Register, a
128 character ASCII decoder and
the refresh circuitry necessary
to synchronize the decoding and
driving of four 5 x 7 dot matrix
displays.
Four 7 bit ASCII words are stored
in the Character RAM. The IC
reads the ASCII data and decodes
it via the 128 character ASCII
decoder. The ASCII decoder
includes the 64 character set of
the HPDL-2416, 32 lower case
ASCII symbols, and 32 foreign
language symbols.
A 5 bit word is stored in the
Control Register. Three fields
within the Control Register
provide an 8 level brightness
control, master blank, and
extended functions disable.
For each display digit location,
two bits are stored in the Attribute
RAM. One bit is used to enable
a cursor character at each digit
location. A second bit is used to
individually disable the blanking
features at each digit location.
The display is blanked and
dimmed through an internal
blanking input on the row drivers.
Logic within the IC allows the user
to dim the display either through
the BL input or through the
brightness control in the control
register. Similarly the display can
be blanked through the BL input,
the Master Blank in the Control
Register, or the Digit Blank
Disable in the Attribute RAM.
Write
(WR, pin 9)
Address Inputs
(A
1
and A
0
, pins
7 and 8)
Data Inputs (D
0
-D
6
,
pins 16 – 22)
V
DD
(pin 6)
GND (pin 12)
Blanking Input
(BL, pin 14)
HP [ AGILENT(HEWLETT-PACKARD) ]
