DDR Termination Regulator
FEATURES
Source and sink current
Low output voltage offset
No external resistors required
Linear topology
Suspend to Ram (STR) functionality
Low external component count
Thermal Shutdown
Available in
SOP8, SOP8-PP Packages
SOP8 / SOP8-PP PKG
TJ2996
APPLICATION
DDR-I, DDR-II and DDR-Ⅲ Termination Voltage
SSTL-2 and SSTL-3 Termination
HSTL Termination
ORDERING INFORMATION
Device
TJ2996D
TJ2996DP
Package
SOP8
SOP8-PP
DESCRIPSION
The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2
and SSTL-3
specifications for
termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent
response to load transients. The output stage prevents shoot through while delivering 1.5A continuous
current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The
TJ2996 also incorporates a V
SENSE
pin to provide superior load regulation and a V
REF
output as a reference
for the chipset and DIMMs. An additional feature found on the TJ2996 is an active low shutdown (
) pin
is pulled low the V
TT
output will tri-state
that provides Suspend To RAM (STR) functionality. When
providing a high impedance output, but, V
REF
will remain active. A power savings advantage can be obtained
in this mode through lower quiescent current.
Absolute Maximum Ratings
CHARACTERISTIC
Supply Voltage to GND
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range
Operating Junction Temperature Range
SYMBOL
PV
IN
AV
IN
V
DDQ
T
SOL
T
STG
T
JOPR
MIN.
-0.3
-0.3
-0.3
-65
-40
MAX.
6.0
6.0
6.0
260
150
125
UNIT
V
℃
℃
℃
Recommended Operation Range
CHARACTERISTIC
AV
IN
to GND
PV
IN
& SDV
IN
to GND
SYMBOL
AV
IN
PV
IN
& SD Input
MIN.
2.3
0
MAX.
5.5
AV
IN
UNIT
V
V
Ordering Information
Package
SOP8
SOP8-PP
Order No.
TJ2996D
TJ2996DP
Description
DDR Termination Regulator
DDR Termination Regulator
1/14
Package Marking
TJ2996
TJ2996
Reel
Reel
Supplied As
Jul. 2010 - Rev. 1.5.3
HTC