DDR Termination Regulator
TJ2996
DESCRIPTION
The TJ2996 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2.
The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to
VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing
shoot through. The TJ2996 also incorporates two distinct power rails that separate the analog circuitry
from the power output stage. This allows a split rail approach to be utilized to decrease internal power
dissipation. It also permits the TJ2996 to provide a termination solution for the next generation of DDR-
SDRAM memory (DDRII). The TJ2996 can also be used to provide a termination voltage for other logic
schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission
across the memory bus. This termination scheme is essential to prevent data error from signal
reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common
form of termination is Class II single parallel termination. This involves one RS series resistor from the
chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms,
although these can be changed to scale the current requirements from the TJ2996. This implementation
can be seen below in Figure 1.
FIGURE 1. SSTL-Termination Scheme
PIN DESCRIPTION
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the TJ2996. AVIN is used to supply all the internal control
circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to
create VTT. These pins have the capability to work off separate supplies depending on the application.
Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON
limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power
loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise
would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing
the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal
to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to
prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction
temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the
manual shutdown where VTT is tri-stated and VREF remains active.
Jul. 2010 - Rev. 1.5.3
6/14
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
