DDR VDDQ and VTT Termination Voltage Regulator
APPLICATION INFORMATION
TJ3212
Powering DDR Memory
Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and
graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two
memory accesses per cycle versus one. DDR SDRAMs transmit data at both the rising and falling edges of the
memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection,
while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power
management architecture than previous RAM technology.
Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all
interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power
consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series
Terminated Logic (SSTL_2), and by the use of a termination voltage, V
TT
. SSTL_2 is an industry standard defined
in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission
reflections. JEDEC further defines the DDR SDRAM specification in JESD79C.
DDR memory requires three tightly regulated voltages: V
DDQ
, V
TT
, and V
REF
(see Figure 1). In a typical SSTL_2
receiver, the higher current V
DDQ
supply voltage is normally 2.5V with a tolerance of ±200mV. The active bus
termination voltage, V
TT
, is half of V
DDQ
. V
REF
is a reference voltage that tracks half of V
DDQ
±1%, and is compared
with the V
TT
terminated signal at the receiver. V
TT
must be within ± 40mV of V
REF
.
Figure 1. Typical DDR terminations, Class II
The V
TT
power requirement is proportional to the number of data lines and the resistance of the termination
resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may
momentarily consume 16.2mA to achieve the 405mV minimum over V
TT
needed at the receiver:
I
terminatio n
=
405mV
= 16.2mA
R
t
(25
Ω
)
A typical 64Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum V
TT
supply
current up to ± 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur
for short durations, if they ever occur at all. These high current peaks can be handled by the V
TT
external capacitor.
In a real memory system, the continuous average V
TT
current level in normal operation is less than ± 200mA.
Mar. 2011 - Preliminary
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9
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HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
