欢迎访问ic37.com |
会员登录 免费注册
发布采购

GM71C17403C 参数 Datasheet PDF下载

GM71C17403C图片预览
型号: GM71C17403C
PDF下载: 下载PDF文件 查看货源
内容描述: 4,194,304字× 4位CMOS动态RAM [4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM]
分类和应用:
文件页数/大小: 10 页 / 100 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
 浏览型号GM71C17403C的Datasheet PDF文件第1页浏览型号GM71C17403C的Datasheet PDF文件第2页浏览型号GM71C17403C的Datasheet PDF文件第4页浏览型号GM71C17403C的Datasheet PDF文件第5页浏览型号GM71C17403C的Datasheet PDF文件第6页浏览型号GM71C17403C的Datasheet PDF文件第7页浏览型号GM71C17403C的Datasheet PDF文件第8页浏览型号GM71C17403C的Datasheet PDF文件第9页  
GM71C(S)17403C/CL
DC Electrical Characteristics
(V
CC
= 5.0V+/-10%, V
SS
= 0V, T
OPR
= 0 ~ 70C)
Symbol
V
OH
V
OL
I
CC1
Parameter
Output Level
Output "H" Level Voltage (I
OUT
= -2mA
)
Output Level
Output "L" Level Voltage (I
OUT
=
2
mA)
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling
:
t
RC
=
t
RC
min)
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = V
IH
,
D
OUT
=
High-Z)
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
RC
= t
RC
min)
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(t
HPC
= t
HPC
min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= V
CC
- 0.2V, D
OUT
= High-Z)
CAS-before-RAS Refresh Current
(t
RC
= t
RC
min)
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
50ns
60ns
70ns
Min
2.0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
V
CC
0.4
120
110
100
2
100
90
80
90
80
70
1
150
100
90
80
350
Unit
V
V
Note
mA
1, 2
I
CC2
mA
I
CC3
mA
2
I
CC4
mA
1, 3
I
CC5
mA
uA
mA
5
I
CC6
I
CC7
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, t
RC
= 62.5us
,
t
RAS
<=
0.3
us,
D
OUT
=
High-Z, CMOS interface)
Standby Current RAS = V
IH
CAS = V
IL
D
OUT
=
Enable
Input Leakage Current
Any Input (0V
<=
V
IN
<=
6V)
Output Leakage Current
(D
OUT
is Disabled, 0V
<=
V
OUT
<= 6
V)
uA
4,5
I
CC8
-
5
mA
1
I
L(I)
I
L(O)
-10
-10
10
10
uA
uA
Note: 1. I
CC
depends on output load condition when the device is selected.
I
CC
(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = V
IL
.
3. Address can be changed once or less while CAS = V
IH
.
4. CAS = L (<=0.2) while RAS = L (<=0.2).
5. L-version.
Rev 0.1 / Apr’01