GM71C18163C
GM71CS18163CL
Self Refresh Mode ( L-version )
Symbol
Parameter
RAS Pulse Width(Self-Refresh)
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
GM71CS18163
CL-5
GM71CS18163
CL-6
GM71CS18163
CL-7
Unit
us
ns
ns
Note
29
Min Max
Min Max Min Max
100
110
-50
-
-
-
100
130
-50
-
-
-
t
RASS
t
RPS
t
CHS
100
90
-50
-
-
-
Notes :
1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200us is required after power followed by a minimum of eight initializa-
tion cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS
refresh).
3. Operation with the t
RCD
(max) limit insures that t
RAC
(max) can be met, t
RCD
(max) is
specified as a reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, then
access time is controlled exclusively by t
CAC
.
4. Operation with the t
RAD
(max) limit insures that t
RAC
(max) can be met, t
RAD
(max) is
specified as a reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, then
access time is controlled exclusively by t
AA
.
5. Either t
ODD
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
RCD
<= t
RCD
(max) and t
RAD
<= t
RAD
(max). If t
RCD
or t
RAD
is greater than the
maximum recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1TTL loads and 100pF.
10. Assumes that t
RCD
>= t
RCD
(max) and t
RAD
<= t
RAD
(max).
11. Assumes that t
RCD
<= t
RCD
(max) and t
RAD
>= t
RAD
(max).
12. Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13. t
OFF
(max) and t
OEZ
(max) define the time at which the outputs achieve the open circuit condi-
tion and are not referred to output voltage levels.
14. t
WCS,
t
RWD
, t
CWD
, t
AWD
and t
CPW
are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if t
WCS
>= t
WCS
(min), the cycle is an early
write cycle and the data out pin will remain open circuit(high impedance) throughout the
entire cycle; if t
RWD
>=t
RWD
(min), t
CWD
>=t
CWD
(min), and t
AWD
>=t
AWD
(min), or t
CWD
>=t
CWD
(min)
t
AWD
>= t
AWD
(min) and t
CPW
>= t
CPW
(min), the cycle is a read-modify-write and the data out-
put will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
Rev 0.1 / Apr’01
HYNIX [ HYNIX SEMICONDUCTOR ]
