GM71C(S)17400C/CL
Notes:
1. AC Measurements assume t
T
=5ns.
2. An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
3. Operation with the
t
RCD
(max) limit insures that
t
RAC
(max) can be met,
t
RCD
(max) is specified as a
reference point only; if
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is
controlled exclusively by
t
CAC
.
4. Operation with the
t
RAD
(max) limit insures that
t
RAC
(max) can be met,
t
RAD
(max) is specified as a
reference point only; if
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is
controlled exclusively by
t
AA
.
5. Either t
ODD
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between V
IH
(min) and V
IL
(max).
8. Assume that
t
RCD
<=
t
RCD
(max) and
t
RAD
<=
t
RAD
(max). If
t
RCD
or
t
RAD
is greater than the maximum
recommended value shown in this table,
t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 2 TTL loads and 100pF. (V
OH
= 2.4V, V
OL
= 0.8V)
10. Assume that
t
RCD
>=
t
RCD
(max) and
t
RCD +
t
CAC
(max) >=
t
RAD +
t
AA
(max).
11. Assume that
t
RAD
>=
t
RAD
(max) and
t
RCD +
t
CAC
(max) <=
t
RAD +
t
AA
(max).
12. Either
t
RCH
or
t
RRH
must be satisfied for a read cycles.
13.
t
OFF
(max) and
t
OEZ
(max) define the time at which the outputs achieve the open circuit condition
and are not referenced to output voltage levels.
14.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPW
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if
t
WCS
>=
t
WCS
(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
RWD
>=
t
RWD
(min),
t
CWD
>=
t
CWD
(min), and
t
AWD
>=
t
AWD
(min), or
t
CWD
>=
t
CWD
(min),
t
AWD
>=
t
AWD
(min) and
t
CPW
>=
t
CPW
(min), the cycle is a read-modify-write and the data output will contain
data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16.
t
RASP
defines RAS pulse width in Fast page mode cycles.
17. Access time is determined by the longest among
t
AA
or
t
CAC
or
t
ACP
.
Rev 0.1 / Apr’01
HYNIX [ HYNIX SEMICONDUCTOR ]
