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GM71S17403CL-6 参数 Datasheet PDF下载

GM71S17403CL-6图片预览
型号: GM71S17403CL-6
PDF下载: 下载PDF文件 查看货源
内容描述: 4,194,304字× 4位CMOS动态RAM [4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM]
分类和应用:
文件页数/大小: 10 页 / 100 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
 浏览型号GM71S17403CL-6的Datasheet PDF文件第1页浏览型号GM71S17403CL-6的Datasheet PDF文件第2页浏览型号GM71S17403CL-6的Datasheet PDF文件第3页浏览型号GM71S17403CL-6的Datasheet PDF文件第5页浏览型号GM71S17403CL-6的Datasheet PDF文件第6页浏览型号GM71S17403CL-6的Datasheet PDF文件第7页浏览型号GM71S17403CL-6的Datasheet PDF文件第8页浏览型号GM71S17403CL-6的Datasheet PDF文件第9页  
GM71C(S)17403C/CL  
Capacitance (VCC = 5V+/-10%, TA = 25C)  
Symbol  
CI1  
Parameter  
Input Capacitance (Address)  
Input Capacitance (Clocks)  
Output Capacitance (Data-In/Out)  
Min  
Max  
Unit  
pF  
Note  
1
-
-
-
5
7
7
CI2  
pF  
1
CI/O  
pF  
1, 2  
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.  
2. CAS = VIH to disable DOUT  
.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 2, 18, 19)  
Test Conditions  
Input rise and fall times: 2 ns  
Input timing reference levels: 0.8V, 2.4V  
Output timing reference levels: 0.8V, 2.0V  
Output load : 1 TTL gate + C (100pF)  
(Including scope and jig)  
L
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)  
GM71C(S)17403 GM71C(S)17403 GM71C(S)17403  
C/CL-5  
C/CL-6  
C/CL-7  
Unit Note  
Symbol  
Parameter  
Min Max Min Max Min Max  
Random Read or Write Cycle Time  
RAS Precharge Time  
84  
30  
-
-
104  
40  
-
-
124  
50  
-
-
ns  
ns  
t
RC  
tRP  
CAS Precharge Time  
7
-
10  
60  
-
13  
70  
-
ns  
t
CP  
ns  
ns  
ns  
ns  
21  
22  
t
RAS  
CAS  
ASR  
RAH  
ASC  
CAH  
RCD  
RAD  
RSH  
CSH  
CRP  
ODD  
DZO  
DZC  
RAS Pulse Width  
50 10,000  
7 10,000  
10,000  
10,000  
t
CAS Pulse Width  
10 10,000  
13 10,000  
t
Row Address Set up Time  
Row Address Hold Time  
Column Address Set-up Time  
0
7
0
7
-
-
-
-
0
10  
0
-
-
-
-
0
10  
0
-
-
-
-
t
t
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Column Address Hold Time  
RAS to CAS Delay Time  
RAS to Column Address Delay Time  
RAS Hold Time  
10  
13  
11 37  
14 45  
12 30  
14 52  
12 35  
3
4
t
t
9
10  
35  
5
25  
-
t
13  
40  
5
-
-
13  
45  
5
-
-
24  
CAS Hold Time  
-
t
CAS to RAS Precharge Time  
OE to DIN Delay Time  
-
-
-
t
t
13  
0
-
15  
0
-
18  
0
-
5
6
6
7
t
OE Delay Time from DIN  
CAS Delay Time from DIN  
Transition Time (Rise and Fall)  
-
-
-
0
-
0
-
0
-
t
tT  
2
50  
2
50  
2
50  
Rev 0.1 / Apr’01