GM76C256CL/LL
32,768 WORDS x 8 BIT
CMOS STATIC RAM
Description
The GM76C256C family is a 262,144 bits static
random access memory organized as 32,768 words
by 8 bits. Using a 0.6um advanced CMOS tech-
nology and operated a single 5.0V supply.
Advanced circuit techniques provide both high
speed and low power consumption. The Family
can support various operating temerature ranges
for user flexibility of system design.
The Family has Chip select /CS, which allows for
device selection and data retention control, and
output enable (/OE), which provides fast memory
access. Thus it is suitable for high speed and low
power applications, particularly where battery
back-up is required.
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Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O7
I/O6
I/O5
I/O4
I/O3
Features
* High Speed : Fast Access and Cycle Time
55/70ns Max
* Low Power Standby and Low Power Operation
-Standby : 165uW at T
A
= -25 ~ 85C (LLE)
110uW at T
A
= 0 ~ 70C (LL)
-Operation : 385mW at Vcc=5.0V + 0.5V
* Completely Static RAM : No Clock or Timing
strobe required
* Power Supply Voltage : 5.0V + 0.5V
* Low Data Retention Voltage : 2.0V(Min)
* Temperature Range
-GM76C256CL/LL : ( 0 ~ 70C)
-GM76C256CLE/LLE : (-25 ~ 85C)
* Package Type : JEDEC Standard 28 SOP,TSOP(I)
(Top View)
Block Diagram
A0
A1
A2
Address
Buffer
64 x 8
A13
A14
6
Y
Decoder
64
........
9
X
Decoder
512
MEMORY CELL ARRAY
512 x 64 x 8
(32K x 8)
Column Select
Pin Description
Pin
A0-A14
/WE
/OE
/CS
I/O0-I/O7
V
CC
V
SS
Function
Address Inputs
Write Enable Input
Output Enable Input
Chip Select Input
Data Input/Output
Power Supply
Ground
/OE
/WE
/CS
Chip
Control
8
I/O
Control
I/O Buffer
I/O1
I/O2
I/O3
I/O5
I/O6
I/O0
I/O4
33
I/O7
HYNIX [ HYNIX SEMICONDUCTOR ]
