GMM2739233ETG
Relationship Between Frequency and Minimum Latency
-7
-75
-8
-7K
-7J
Parameter
143 100 133 100 125 100 100 100 100 66
frequency(MHz)
Symbol
Notes
7
3
10 7.5 10
8
3
10 10 10 10 15
t
CK (ns)
Active command to column
command (same bank)
Active command to active
command (same bank)
Active command to Precharge
command (same bank)
Precharge command to active
command (same bank)
Write recovery or last data-in to
Precharge command (same bank)
Active command to active
command (different bank)
2
7
5
2
1
3
9
6
3
1
2
7
5
2
1
2
7
5
2
1
2
7
5
2
1
2
7
5
2
1
2
7
5
2
1
2
6
4
2
1
1
l
l
RCD
= [lRAS
+lRP], 1
9
6
3
1
9
6
3
1
l
RC
1
1
1
1
RAS
l
RP
l
RWL
2
1
4
2
1
3
2
1
4
2
1
3
2
1
4
2
2
3
2
1
3
2
1
3
2
1
3
2
2
3
l
RRD
Self refresh exit time
l
SREX
Last data in to active command
(Auto Precharge, same bank)
Self refresh exit to command
input
= [lRWL
+lRP], 1
l
APW
9
7
9
7
9
7
7
7
7
6
= [lRC]
l
SEC
Precharge
command to
high impedance
-
2
3
-
2
3
-
2
3
2
3
2
3
-
2
3
(CL=2)
l
l
HZP
3
3
3
3
(CL=3)
HZP
Last data out to active
command
(auto Precharge) (same bank)
1
1
1
-
1
1
1
1
1
1
-
1
l
APR
Last data out to
Precharge
(early Precharge)
-
-1
-1
-2
-
-1 - 1 - 1
-1
(CL=2)
l
EP
EP
-2
-2 -2
-2
-2 - 2 - 2 - 2 - 2
(CL=3)
l
Column command to column
command
Write command to data in
latency
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
l
CCD
l
WCD
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
0
2
1
1
0
DQM to data in
l
DID
DQM to data out
l
DOD
CKE to CLK disable
Register set to active command
CS to command disable
l
l
CLE
RSA
l
CDD
Power down exit to command
input
1
1
1
1
1
1
1
1
1
1
l
PEC
Rev. 1.1/Apr.01
11
HYNIX [ HYNIX SEMICONDUCTOR ]
