GMS81C2112/GMS81C2120
Example 1:
Timer0 = 16-bit timer mode, 0.5s at 4MHz
LDM
LDM
LDM
LDM
SET1
EI
:
:
TM0,#0000_1111B;8uS
TM1,#0100_1100B;16bit Mode
TDR0,#<62500
;8uS X 62500
TDR1,#>62500
;=0.5s
T0E
Example 3:
Timer0 = 16-bit capture mode
LDM
LDM
LDM
LDM
LDM
LDM
SET1
EI
:
:
R0FUNC,#0000_0001B;INT0 set
TM0,#0010_1111B;Capture Mode
TM1,#0100_1100B;16bit Mode
TDR0,#<0FFH
;
TDR1,#>0FFH
;
IEDS,#01H;Falling Edge
T0E
Example 2:
Timer0 = 16-bit event counter mode
LDM
LDM
LDM
LDM
LDM
SET1
EI
:
:
R0FUNC,#0000_0100B;EC0 Set
TM0,#0001_1111B;Counter Mode
TM1,#0100_1100B;16bit Mode
TDR0,#<0FFH
;
TDR1,#>0FFH
;
T0E
12.6 PWM Mode
The GMS81C2120 has a high speed PWM (Pulse Width
Modulation) functions which shared with Timer1.
In PWM mode, pin R56/PWM1O/T1O outputs up to a 10-
bit resolution PWM output. This pin should be configured
as a PWM output by setting "1" bit PWM1O in R5FUNC.6
register.
The period of the PWM output is determined by the
T1PPR (PWM1 Period Register) and PWM1HR[3:2]
(bit3,2 of PWM1 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM1 Duty Regis-
ter) and PWM1HR[1:0] (bit1,0 of PWM1 High Register).
The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM1HR[3:2].
And writes duty value to the T1PDR and the
PWM1HR[1:0] same way.
The T1PDR is configured as a double buffering for glitch-
less PWM output. In Figure 12-12, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle)
PWM Period = [PWM1HR[3:2]T1PPR] X Source Clock
PWM Duty
= [PWM1HR[1:0]T1PDR] X Source Clock
The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
JUNE. 2001 Ver 1.00
53
HYNIX [ HYNIX SEMICONDUCTOR ]
