GMS90C320
CPU
The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD
arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con-
sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are
executed in 1.0µs.
Special Function Register PSW
MSB
7
LSB
0
Bit No.
6
5
4
3
2
1
Addr. D0H
CY
AC
F0
RS1
RS2
OV
F1
P
PSW
Bit
Function
CY
AC
F0
Carry Flag
Auxiliary Carry Flag (for BCD operation)
General Purpose Flag
Register Bank select control bits
Bank 0 selected, data address 00H -07H
Bank 1 selected, data address 08H -0FH
Bank 2 selected, data address 10H -17H
Bank 3 selected, data address 18H -1FH
RS1
RS0
0
0
1
1
0
1
0
1
OV
F1
P
Overflow Flag
General Purpose Flag
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/
even number of “one” bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H .
OCT. 2000 Ver 1.2
9
HYNIX [ HYNIX SEMICONDUCTOR ]
