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GMS97L51 参数 Datasheet PDF下载

GMS97L51图片预览
型号: GMS97L51
PDF下载: 下载PDF文件 查看货源
内容描述: HYNIX SEMICONDUCTOR INC 。 8位单芯片微控制器 [HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS]
分类和应用: 微控制器
文件页数/大小: 59 页 / 794 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GMS90 Series
PIN DEFINITIONS AND FUNCTIONS
Pin Number
Symbol
P1.0-P1.7
PLCC-
44
PDIP-
40
MQFP-
44
Input/
Output
I/O
Function
Port1
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of
the pulls-ups (I
IL
, in the DC characteristics). Pins P1.0
and P1.1 also. Port1 also receives the low-order
address byte during program memory verification.
Port1 also serves alternate functions of Timer 2.
P1.0 / T2 :
Timer/counter 2 external count input
P1.1 / T2EX : Timer/counter 2 trigger input
In GMS9XC54/56/58:
P1.0 / T2, Clock Out : Timer/counter 2 external count
input, Clock Out
2-9
1-8
40-44,
1-3
2
3
1
2
40
41
2
P3.0-P3.7
11,
13-19
1
10-17
40
5, 7-13
I/O
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 3 pins that are
externally pulled low will source current because of
the pulls-ups (I
IL
, in the DC characteristics). Port 3 also
serves the special features of the 80C51 family, as
listed below.
P3.0 / RxD
receiver data input (asynchronous) or
data input output(synchronous) of serial
interface 0
transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0
interrupt 0 input/timer 0 gate control
interrupt 1 input/timer 1 gate control
counter 0 input
counter 1 input
the write control signal latches the data
byte from port 0 into the external data
memory
the read control signal enables the
external data memory to port 0
11
10
5
13
11
7
P3.1 / TxD
14
15
16
17
18
12
13
14
15
16
8
9
10
11
12
P3.2 /INT0
P 3.3 / IN T 1
P3.4 /T0
P3.5 /T1
P3.6 / WR
19
XTAL2
20
17
18
13
14
O
P3.7 /RD
XTAL2
Output of the inverting oscillator amplifier.
8
Oct. 2000 Ver 3.1a