11
256Mbit (8Mx32bit) Mobile SDR
H55S2622JFR Series
H55S2532JFR Series
FEATURES
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Standard SDRAM Protocol
Clock Synchronization Operation
- All the commands registered on positive edge of basic input clock (CLK)
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MULTIBANK OPERATION - Internal 4bank operation
- During burst Read or Write operation, burst Read or Write for a different bank is performed.
- During burst Read or Write operation, a different bank is activated and burst Read or Write for that bank is per-
formed
- During auto precharge burst Read or Write, burst Read or Write for a different bank is performed
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Power Supply Voltage: V
DD
= 1.8V, V
DDQ
= 1.8V
LVCMOS compatible I/O Interface
Low Voltage interface to reduce I/O power
Programmable burst length: 1, 2, 4, 8 or full page
Programmable Burst Type: sequential or interleaved
Programmable CAS latency of 3 or 2
Programmable Drive Strength
Low Power Features
- Programmable PASR(Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Programmable DS (Drive Strength)
- Deep Power Down Mode
Operating Temperature
- Mobile Temp.: -30
o
C
~ 85
o
C
Package Type: 90ball FBGA, 0.8mm pitch (Lead & Halogen Free)
Address Table
Row Address
A0 ~ A11
A0 ~ A12
Column Address
A0 ~ A8
A0 ~ A7
Page Size
2KByte (Normal)
1KByte (Reduced)
Part Number
H55S2622JFR
H55S2532JFR
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Rev 1.0 / Nov. 2008
5
HYNIX [ HYNIX SEMICONDUCTOR ]
