Synchronous DRAM Memory 128Mbit (8Mx16bit)
H57V1262GTR Series
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Parameter
CL = 3
CL = 2
Speed
(MHz)
tCK3
tCK2
tCHW
tCLW
CL = 3
CL = 2
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
200
166
143
133
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
Min Max Min Max Min Max Min Max
5.0
-
1.75
1.75
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
1000
-
-
4.5
-
-
-
-
-
-
-
-
-
-
-
4.5
-
6.0
-
2.0
2.0
-
-
2.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.0
-
-
1000
-
-
5.4
-
-
-
-
-
-
-
-
-
-
-
5.4
-
7.0
-
2.0
2.0
-
-
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
1000
-
-
5.4
-
-
-
-
-
-
-
-
-
-
-
5.4
-
7.5
10
2.5
2.5
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
100
0
-
-
5.4
6.0
-
-
-
-
-
-
-
-
-
-
5.4
6.0
System Clock Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Access Time From Clock
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to Data Output in
High-Z Time
Note:
CL = 3
CL = 2
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to
the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 2.0V. If tR > 1ns, then (tR/2-0.5)ns
should be added to the parameter.
Rev. 1.0 / Aug. 2009
10
HYNIX [ HYNIX SEMICONDUCTOR ]
