Table 5: Intel 80C88A Read Cycle Timing Parameters (Busmode = 1)
Symbol
tsu1
th1
tpw1
td1
tdoz1
tdoz2
Parameter
Input Address and /CE Setup before /RE Inactive
Input Address and /CE Hold after /RE Inactive
/RE Low Duration
Delay from /CE to DTACK Active
Delay from /RE Inactive to DTACK in Tristate Mode
Delay from /RE Inactive to HI_DATA [7:0] Tristate Mode
Min.
35
5
200
-
-
10
Max.
-
-
-
35
10
-
Unit
ns
ns
ns
ns
ns
ns
HI_ADDR [4:0]
Valid
/CE
t
pw1
/RE
t
d1
Z
t
h1
Z
DTACK
t
doz1
HI_DATA[7:0]
t
su1
F
IGURE
3: I
NTEL
80C88A R
EAD
T
IMING
D
IAGRAM
Note: HI_ADDR[4:0] is derived from the processor(80C88A) A15-A8 bus and HI_DATA[7:0] is
connected to the AD7 - AD0 bus.
t
doz2
#This page is only for HDM8513AP.
10
HYNIX [ HYNIX SEMICONDUCTOR ]
