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HY29F800ABG-70 参数 Datasheet PDF下载

HY29F800ABG-70图片预览
型号: HY29F800ABG-70
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1Mx8 / 512Kx16 ) , 5伏只,闪存 [8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 40 页 / 263 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY29F800A
8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n
High Performance
– Access times as fast as 50 ns
n
Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 35 mA typical program/erase current
– 5 µA maximum CMOS standby current
n
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and fifteen 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
n
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F800A is an 8 Megabit, 5 volt only CMOS
Flash memory organized as 1,048,576 (1M) bytes
or 524,288 (512K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F800A can be programmed and erased
in-system with a single 5-volt V
CC
supply. Internally
generated and regulated voltages are provided for
program and erase operations, so that the device
does not require a high voltage power supply to
perform those functions. The device can also be
programmed in standard EPROM programmers.
Access times as fast as 55 ns over the full operat-
ing voltage range of 5.0 volts ± 10% are offered for
timing compatibility with the zero wait state require-
ments of high speed microprocessors. A 50 ns
Preliminary
Revision 1.1, February 2002
n
Sector Protection
– Any combination of sectors may be locked
to prevent program or erase operations
within those sectors
n
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 19 sec typical
n
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n
Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
n
Minimum 100,000 Program/Erase Cycles
n
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
LOGIC DIAGRAM
19
A[18:0]
DQ[7:0]
7
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
DQ[14:8]
DQ[15]/A-1
8